Fast-track setup for multi-FPGA prototyping.The HES-DVM aids in design partitioning, clock conversion and mapping to FPGA and facilitates designing inter-chip connections that utilize serialization techniques to overcome limitation of FPGA I/O. Physical prototyping enables the highest clock rates, often close to the target ones, so it is ideal for verification in the real environment with devices sending and receiving real data streams. HW Debugger tool with GUI to manage debug process.Memory back-door access for read & write.Saving debug data in waveform files: ASDB for Riviera-PRO and FSDB for Verdi.HVD technology for 100% visibility with reduced number of captured probes.Self-constrained and automated FPGA implementation using vendor tools (Xilinx Vivado).Automatic code instrumentation for debugging.Memory flow to map design memories to board or FPGA resources.Automatic gated clock conversion with unlimited number of clock domains.Automatic partitioning and inter-FPGA connections.Incremental design synthesis with third party synthesis tools.Behavioral transactors compiler supporting SV DPI-C and SCE-MI SV-Connect.Design compilation for SystemVerilog, Verilog and VHDL.Easy integration with SystemVerilog, VHDL, SystemC, C/C++.SCE-MI and TLM for transaction level co-emulation.SystemVerilog DPI-C for transaction level and UVM simulation acceleration.Simulation acceleration (Aldec simulators or third party simulators).
Third party or in-house made custom boards.Also included are powerful debugging tools that allow for 100% visibility into modules running in the FPGA, making the HES-DVM emulation platform as easy to use as an RTL simulator. These use models enable many applications such as hardware and software co-verification utilizing TLM wrappers and high-speed AXI or AHB bus transactors to connect design residing in hardware with Virtual Platforms. HES-DVM™ provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.Įmulation modes include simulation acceleration, transaction level co-emulation and in-circuit emulation for chip and system level verification of SoC and ASIC designs. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs.
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